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1 of 11 121907 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 512k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? low-power cmos ? read and write access times as fast as 100ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? optional industrial temperature range of - 40 c to +85 c, designated ind ? jedec standard 32-pin dip package ? powercap module (pcm) package ? directly surface-mountable module ? replaceable snap-on powercap provides lithium backup battery ? standardized pinout for all nonvolatile sram products ? detachment feature on pcm allows easy removal using a regular screwdriver pin assignment pin description a0 - a18 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+3.3v) gnd - ground nc - no connect ds1250w 3.3v 4096k nonvolatile sram www.maxim-ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32-pin encapsulated package 740-mil extended a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a18 dq2 gnd 15 16 18 17 dq4 dq3 w e nc a15 a16 nc v cc oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 gnd v bat 34-pin powercap module (pcm) (uses ds9034pc powercap)
ds1250w 2 of 11 description the ds1250w 3.3v 4096k nonvolatile sram is a 4,194,304-bit, fully sta tic, nonvolatile sram organized as 524,288 words by 8 bits. each nv sram has a self-contained lithium energy source and control circuitry, which constantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. dip-package ds 1250w devices can be used in place of existing 512k x 8 static rams directly conforming to the popular bytewide 32-pin dip standa rd. ds1250w devices in the powercap module package are di rectly surface mountab le and are normally paired with a ds9034pc powercap to form a complete nonvolatile sram module. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required fo r microprocessor interfacing. read mode the ds1250w executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the uni que address specified by the 19 address inputs (a 0 - a 18 ) defines which of the 524,288 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be meas ured from the later-occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1250w executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later-occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier ri sing edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be ke pt inactive (hig h) during write cycles to avoid bus contention. however, if the output driv ers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1250w provides full functional capability for v cc greater than 3.0 volts and write protects by 2.8 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become ?don?t care,? and all outputs become high-impedance. as v cc falls below approximately 2.5 volts, a power switchi ng circuit connects the li thium energy source to ram to retain data. during power-up, when v cc rises above approximate ly 2.5 volts, the power switching circuit connects external v cc to ram and disconnects the lith ium energy source. normal ram operation can resume after v cc exceeds 3.0 volts. freshness seal each ds1250w device is shipped from dallas se miconductor with its li thium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 3.0 volts, the lithium energy source is enabled for battery back-up operation. packages the ds1250w is available in two packages: 32-pin dip and 34-pin powercap module (pcm). the 32- pin dip integrates a lithium batter y, an sram memory and a nonvolatile control function into a single package with a jedec-standard 600-mil dip pinout . the 34-pin powercap module integrates sram
ds1250w 3 of 11 memory and nonvolatile control into a module base al ong with contacts for c onnection to the lithium battery in the ds9034pc powercap. the powercap module package design allows a ds1250w pcm device to be surface m ounted without subjecting its lithium backup battery to destructive high- temperature reflow soldering. af ter a ds1250w module base is refl ow soldered, a ds9034pc powercap is snapped on top of the base to form a complete nonvolatile sram module. the ds9034pc is keyed to prevent improper attachme nt. ds1250w module bases and ds9034pc powercaps are ordered separately and shipped in separate containers. see th e ds9034pc data sheet for further information. absolute maxi mum ratings* voltage on any pin relative to ground -0.3v to +4.6v operating temperature 0c to 70c, -40c to +85c for ind parts storage temperature -40c to +70c, -40c to +85c for ind parts soldering temperature dip module +260c for 10 seconds caution: do not reflow (wave or hand solder only) powercap module see ipc/jedec j-std-020 * this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the opera tion sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. recommended dc oper ating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 3.0 3.3 3.6 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.4 v dc electrical characteristics (t a : see note 10) (v cc =3.3v 0.3v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.2v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 50 250 a standby current ce =v cc -0.2v i ccs2 30 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v capacitance ( t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
ds1250w 4 of 11 ac electrical characteristics (t a : see note 10) (v cc =3.3v 0.3v) ds1250w-100 DS1250W-150 parameter symbol min max min max units notes read cycle time t rc 100 150 ns access time t acc 100 150 ns oe to output valid t oe 50 70 ns ce to output valid t co 100 150 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 35 35 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 100 150 ns write pulse width t wp 75 100 ns 3 address setup time t aw 0 0 ns write recovery time t wr1 t wr2 5 20 5 20 ns 12 13 output high z from we t odw 35 35 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 40 60 ns 4 data hold time t dh1 t dh2 0 20 0 20 ns 12 13 read cycle see note 1
ds1250w 5 of 11 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 12
ds1250w 6 of 11 power-down/power-up condition power-down/power-up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a =25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of a ny amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high-impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high-impedance state during this period.
ds1250w 7 of 11 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high -impedance state during this period. 9. each ds1250w has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical charac teristics are valid over the full operating temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power-down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1250 modules are recognized by u nderwriters laboratory (u.l. ? ) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0 to 2.7v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part number temperature range supply tolerance pin/package speed grade ds1250w-100 0c to +70c 3.3v 0.3v 32 / 740 emod 100ns ds1250w-100+ 0c to +70c 3.3v 0.3v 32 / 740 emod 100ns ds1250wp-100 0c to +70c 3.3v 0.3v 34 / powercap* 100ns ds1250wp-100+ 0c to +70c 3.3v 0.3v 34 / powercap* 100ns ds1250w-100ind -40c to +85c 3.3v 0.3v 32 / 740 emod 100ns ds1250w-100ind+ -40c to +85c 3.3v 0.3v 32 / 740 emod 100ns ds1250wp-100ind -40c to +85c 3.3v 0.3v 34 / powercap* 100ns ds1250wp-100ind+ -40c to +85c 3.3v 0.3v 34 / powercap* 100ns DS1250W-150 0c to +70c 3.3v 0.3v 32 / 740 emod 150ns DS1250W-150+ 0c to +70c 3.3v 0.3v 32 / 740 emod 150ns ds1250wp-150 0c to +70c 3.3v 0.3v 34 / powercap* 150ns ds1250wp-150+ 0c to +70c 3.3v 0.3v 34 / powercap* 150ns + denotes lead-free/rohs-compliant product. * ds9034pc or ds9034pci (powercap) requi red. must be ordered separately. package information (for the latest package outline information, go to http://www.maxim-ic.com/dallaspackinfo .) package type document no. 32 dip 56-g0002-001
ds1250w 8 of 11 ds1250w nonvolatile sram, 34-pin powercap module inches pkg dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030
ds1250w 9 of 11 ds1250w nonvolatile sram, 34-pin powercap module with powercap inches pkg dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 assembly and use reflow soldering dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented label-side up (live-bug). hand soldering and touch-up do not touch soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove part, apply flux, heat pad until solder reflows, and use a solder wick. lpm replacement in a socket to replace a low profile module in a 68-pin plcc socket, attach a ds9034pc powercap to a module base then insert the complete module into the so cket one row of leads at a time, pushing only on the corners of the cap. never apply force to the center of the device. to remove from a socket, use a plcc
ds1250w 10 of 11 extraction tool and ensure that it does not hit or da mage any of the module ic components. do not use any other tool for extraction. recommended powercap module land pattern inches pkg dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 - recommended powercap mo dule solder stencil inches pkg dim min nom max a - 1.050 - b - 0.890 - c - 0.050 - d - 0.030 - e - 0.080 -
ds1250w 11 of 11 revision history revision date description pages changed 121907 added package information table. removed the dip module package drawing and dimension table. 7, 8

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